1. Field of the Invention
An embodiment of this disclosure relates to a semiconductor device and a method of programming the same and, more particularly, to a semiconductor device and a method of programming the same, which reduce interference between adjacent cells in a program operation.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a memory cell array for illustrating the problems of a known program operation.
The memory cell array of a NAND flash memory device, from among semiconductor devices, is described below with reference to FIG. 1.
A memory cell array of a NAND flash memory device includes a plurality of memory blocks. Each of the memory blocks includes memory strings STe and STo. Each of the memory strings STe and STo includes a drain select transistor, a plurality of memory cells, and a source select transistor which are coupled in series. The gates of drain select transistors included in different memory strings STe and STo are coupled to a common drain select line DSL, and gates of the source select transistors included in different memory strings STe and STo are coupled to a common source select line SSL. Furthermore, in different memory strings STe and STo, gates of memory cells included in the same row are coupled to respective word lines WLn−k to WLn+k corresponding to the row.
When a program operation is started, all memory cells included in a selected memory block are erased and the erased memory cells are programmed by page (that is, a group of memory cells coupled to the same word line). In order to suppress interference between adjacent memory strings STe and STo occurring when the erased memory cells are programmed, the memory strings are divided into even memory strings STe and odd memory strings STo, and a program operation is performed on the even memory strings STe and then on the odd memory strings STo. That is, if the even memory strings STe are selected and programmed, the odd memory strings STo are not programmed.
In order to suppress interference between adjacent memory cells, a program operation using an Incremental Step Pulse (hereinafter referred to as an ‘ISPP’) method may be performed by gradually raising a program voltage.
Although the odd or even memory strings are selected and a program operation using an ISPP method is performed as described above, interference 2ΔX+2ΔY still occurs between adjacent memory cells within the same memory string and adjacent memory cells within the same page.
FIG. 2 is a graph illustrating a shift in threshold voltages according to the known program operation.
Referring to FIG. 2, for example, a memory cell 10 coupled to the nth word line WLn and an odd memory string STo is subjected to interferences 2ΔY when two memory cells 22 and 24 included in the same odd memory string STo as the memory cell 10 are programmed, and the memory cell 10 is also subjected to interferences 2ΔX when two memory cells 32 and 34 included in the same word line WLn as the memory cell 10 are programmed. For this reason, the one memory cell 10 is subject to the interferences ‘2ΔX+2ΔY’, thus having a threshold voltage 42 higher than a target threshold voltage 40.